Bus Lab — MCU Playground

Pull-up R

Bus capacitance C

Bus speed

Slave stretches the clock

Analog SCL / SDA: rises are RC curves. A rise that misses V_IH before the next clock loses the bit

τ = R·C—

t_r (10–90 %) = 2.2τ—

Spec limit—

Valid R window—

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Bit rate

Same bus capacitance, two drivers: push-pull charges the bus hard both ways; open-drain can only pull low and waits for the pull-up

Open-drain t_r—

Push-pull t_r (25 Ω)—

Open-drain max—

Push-pull max—

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Master mode

Slave mode

Bit order

Set the slave mode differently from the master to see a mode-mismatch race.

Master byte (MOSI)

Slave byte (MISO)

CS / SCK / MOSI / MISO: green ticks mark sampling points, orange ticks output changes, red marks races

Master sent (MOSI)—

Master received (MISO)—

Slave sent (MISO)—

Slave received (MOSI)—